Really neat! Having a fixed framework to plug accelerator blocks into is lets accelerator designers cut to the chase.

I'd bet the 10ms hit to reconfigure their zynq grows on larger FPGAs...

Edit (Additional Thought): Thus could allow designers significantly smaller/cheaper FPGAs. Rather than statically implement all required functions, intermediate results can be saved in off chip RAM while the next function is loaded. That said it'd require significant additional engineering effort.