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[dupe] Intel Delays Mass Production of 10nm CPUs to 2019 (anandtech.com)
47 points by cm2187 on April 28, 2018 | hide | past | favorite | 16 comments




Thanks!


Can someone who understands the manufacturing and engineering difficulties here explain things for a layman? Are we starting to bump up against physical limitations of what’s even possible, or is this something different?


Not sure if Intel has other problems, but there are limits to how small things can get with a particular wavelength of light. DUV (deep ultraviolet) is at 193nm. They've been able to etch significantly smaller than the wavelength by using immersion (water has a higher index of refraction) and some fancy tricks with multiple exposures under different masks (multi-patterning). But all that had to be done because there were no suitable light sources with shorter wavelength. EUV (extreme ultraviolet) has a wavelength of only 13.5nm so a lot of complexity will go away when it comes on line. However EUV still has some challenges ahead and will probably be deployed slowly. Then, shortly after the introduction of EUV, there are other physical limits around 5nm. The lithography end-game is very near.

It's been really amazing to watch this progression for several decades. The end was declared near a number of times but people always found ways to keep going, but I truly believe it's almost over this time.


What about the single atom transistor?

https://en.wikipedia.org/wiki/Single-atom_transistor

A silicon atom is 0.210nm in size. Even if we cannot each single atoms, we have at least another order of magnitude in die shrinks left. Also, given fabrication companies’ marketing, it would not surprise me if we hear about a 0.13nm fabrication process.


Thanks for the elaboration. Is there also a layman's explanation for the what makes 13.5nm lasers harder to etch with than 193nm lasers?


There are no lenses which are transparent at 13.5. This means you have to use mirrors instead, and even that's a challenge. 13.5nm was selected because it can be reflected by special Molybdenum/Silicon mirrors, but even these mirrors only reflect about 70% of the light. This means that for every two mirrors you add to the system, you have to double the brightness of your energy source.

As I understand it, the EUV light is produced by dropping little drops of tin in front of a laser, which turns it into a plasma that emits 13.5nm light. However, tin particles scatter everywhere and eventually damage the collector mirror, so it's hard to make these machines robust.

I also imagine with these high energies and 30% absorption, you have to cool all the mirrors to keep them from deforming, but I'm no expert.


Radiation at 13nm cannot use normal mirrors or lenses for guiding/focusing the beam. The ones we know of reduce the power significantly such that your light source has to be very powerful. Generating this radiation is not easy.



Given that TSMC just started high volume production of 7nm chips (https://www.anandtech.com/show/12677/tsmc-kicks-off-volume-p...), this sounds bad for Intel.


Not really. Intel 14nm is better than TSMC 10nm. The processes are way way way more complicated than can be distilled down into a single number. And the number has become a marketing number. So yeah, Intel 10nm is perhaps somewhat comparable to TSMC 7nm.

But what is "High volume production" really? This is another marketing term! Intel has produced and sold a couple 10nm chips, though they are hard to find. TSMC 7nm chips are not in any consumer's hands yet. We'll have to wait and see ...


High volume in this case indicates that the product has reach a high level of quality in terms of defects per million and yield. 10nm is probably in the customer sampling phase, HVM means you can go to Best buy and get a 10nm laptop.


We can probably expect 7nm in consumer hands this fall with iPhones. If thats the case, they are probably pretty close to High volume production.


When intel says 10nm is that the same as TSMCs 10nm, or, is TSMCs 7nm the same as intels 7nm process, or are they describing different processes?


They're different processes, and the way Intel describes feature sizes makes their nodes denser then the "equivalent" TSMC node. Probably not 30% denser, though.


Sounds like tsmc has a new customer




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