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>a 1-bit processor isn't very exciting

Very different order of magnitude but wasn't the connection machine single bit based?




The Connection Machine had a very unusual architecture that was sort of 1-bit, but sort of 32-bit. It was a massively parallel computer of the 1980s with 16,384 processing elements. Each processing element handled one bit at at time. But usually each processing element performed arithmetic on a 32-bit value, in a bit-serial fashion.

You can call this a 1-bit processing element, but I think calling it a 32-bit serial processor is more descriptive. Processing data serially using a 1-bit ALU was not uncommon, from the early EDSAC computer to the PDP-8/S minicomputer to the Datapoint 2200 desktop computer, but these are not considered 1-bit computers. The Connection Machine was more flexible with word size than these, so calling it a 32-bit computer isn't quite accurate either.

In any case, the MC14500B didn't have any support for bit-serial operations. (For instance, you want the processor to add the carry from one bit to the next bit to do addition.) Arithmetic was possible on the MC14500B (Turing machine and so forth), but it was very slow, taking 12 instructions per bit to manipulate the sum and carry. The documentation recommended using an external chip if you needed to do arithmetic.

More: http://bitsavers.org/pdf/thinkingMachines/CM2/Architecture_a...


You mention this briefly, but it's worth pointing out that the CM-2 (and, I believe, the CM-1 as well) was indeed a single-bit-at-a-time processor, but the word length was arbitrary, not 32 bits. You could, in *Lisp (and maybe the low-level calls that C* used, I didn't work with that enough to know) define pretty much any bit length you wanted, up to the number of bits on the processor.

They later implemented a floating-point accelerator that worked with 32 of the 1-bit processors in "slice-wise" mode to do 32 (and possibly 64) bit arithmetic, where the word was spread across all 32 processors.

The CM-5 used true 32-bit SPARC processors.

Also, the CM-2 had up to 128k bits per processor, and you could have 64k of them in one CM-2.


How feasible do you think it would be to recreate the connection machine using modern day FPGA's?

I still think it is one of the most interesting computer architectures that ever made it into (low volume) production.


I'm no FPGA expert but I think two problems would be the 4K per-processor memory and the inter-processor communication. You might have routing problems with the Connection Machine's hypercube routing.

Random Connection Machine fact I found on Wikipedia: Maya Lin, who designed the famous Vietnam War memorial in Washington also designed the exterior of the Connection Machine CM-5.




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