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Designing a RISC-V CPU, Part 2: Successfully executing (some) instructions (mcla.ug)
36 points by slyall on March 19, 2021 | hide | past | favorite | 7 comments


Cool stuff. Well presented. Just by coincidence was just reading this yesterday: https://vivonomicon.com/2020/06/13/lets-write-a-minimal-risc...

nMigen is super interesting but I'm still stuck in Xilinx Vivado as a beginner because it makes integrating small cores so easy. Full RISC-V SoC that does something useful in the FPGA part and runs a small version of Linux and programs that call the FPGA part would be super neat.

Seems small RISCV cores can be written very quickly https://github.com/darklife/darkriscv#introduction, but actually making them production hardware take a long time: https://zipcpu.com/zipcpu/2021/03/18/zipos.html


I don't quite get this. Vivado uses Verilog as input. nMigen (and similar tools such as Chisel and SpinalHDL) just write the Verilog for you. You still use Vivado to generate the actual bitstream (assuming you're using an Xilinx FPGA).


From zero to Microblaze inside PetaLinux is a couple of minutes of work (and some waiting around for it to compile) and has plenty of tutorials. nMigen SoC has a Github repo that is "TBD". Maybe I just didn't look deep enough?


Very interesting and accessible!

One comment on terminology... The people who pay the most attention to the topic maintain a distinction between parallelism and concurrency. Parallelism is more than one bit of work getting done at a time. Concurrency is about coordinating everything being done to ensure that the results make sense.

They say "parallelism giveth, concurrency taketh away". Work done on concurrency is overhead, not directly producing results. Sometimes it makes less useful work be done, such a stalling a functional unit while another uses a shared bus, or delivering two results A, B produced in random order in the required order.

Parallelism is associated with the "data plane", concurrency with the "control plane", in systems that use those ideas.

Software people often don't know about the distinction, and use the terms interchangeably. Keeping them distinct helps sharpen thinking about systems affected by it.


> Software people often don't know about the distinction, and use the terms interchangeably

I think YMMV here - in my experience, only (some) software people make this distinction, and hardware people use the terms interchangeably.


Using the distinction gives you a superpower.


This series is also amazing: http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-...

In the end he switches to RISC-V as well




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