Dynamic structures like this are why datasheets may specify waiting a certain time (with clock applied) in reset before beginning operation --- the need to "charge up" the various capacitors to a suitable voltage first. Similarly, it's also one of the reasons for requiring a minimum clock frequency.

I always thought the minimum frequency was due to the usage of DRAM-like registers

There are a lot of different factors going on. For the older chips I look at, pass transistors are used a lot to hold things for one clock cycle, and these need a minimum frequency before the bits leak away. Registers are usually cross-coupled inverters, so they are stable. (Although the 8008 used dynamic registers.) The 8086 uses some dynamic (precharge) logic in its ALU, which needs the clock to keep going, and I hear modern chips use a lot of dynamic logic. The bootstrap drivers in this post will mostly work with a slow frequency, but will lose some of the boost.

Note that you still have setup and hold timing requirements even with completely synchronous and static logic, due to metastability, propagation delay, etc.

The gate drive sort of does act like a temporary DRAM cell, it's presumably only good for a maximum duration of time, hence a minimum clock rate.

I had to learn the hard way about circuits like the superbuffer here, and even more so the H-bridge: real components are not ideal, switching times are not zero, and until you learn that lesson you'll be releasing a lot of smoke.

Great write-up as always, Ken.

This is why microprocessors usually have non-overlapping clock phases, so everything has time to switch and you don't end up with unexpected shorts. Also, the nice thing about reverse-engineering is that I can assume the circuit works; someone else dealt with all the obscure timing issues.

>"...switching times are not zero, and until you learn that lesson you'll be releasing a lot of smoke."

This is particularly spectacular when those babies control motors ;)

It's particularly satisfying when a design doesn't just account for parasitic elements but uses them to advantage.

You mean "fragile". That kind of design likes to break on smallest component type change. It's akin to relying on compiler quirks to make your code work.

Sure, sometimes you don't have a choice due to various constraints but in general it is to be avoided.

Not so much if they are on chip.

It's reliable with discrete components if the parasitic is just backing an external component. For example, a capacitor across a junction contributes most of the capacitance so the capacitance of the junction is just a small parallel capacitance. I agree that it's not good to use a "bare" parasitic in a discrete circuit, unless the circuit is very insensitive to its value.

Surprised they didn't just boost voltage (or just take auxiliary external voltage higher than 5V) in one place then just distribute it

Older chips like the 8080 had multiple supplies (+5, -5, +12), but chips with a single supply were much preferred. They could have generated a higher voltage on-chip, since the 8086 did have a charge pump to generate the negative substrate bias voltage. But distributing an additional voltage rail would be inconvenient when there was just one layer of metal wiring. So it was probably better to use the bootstrap driver (which only used one additional transistor).